1. Field of the Invention
This invention relates to a semiconductor device and, in particular, relates to a calibration circuit adapted for adjusting impedance of an output circuit and to a semiconductor device incorporating such a calibration circuit.
2. Related Art
Recent electronic systems have been speeded up in operation, wherein the data transfer rate between semiconductor devices forming the system has been highly increased. In order to achieve such an ultra high-speed data transfer, a data signal is made to have a small amplitude and, further, the impedance of a transmission line between the semiconductor devices and the output impedance of an output circuit of each semiconductor device are matched together By matching the impedances, the small-amplitude data signal can be transmitted with no distortion to thereby achieve the speedup of the data transfer. If the impedance of the transmission line between the semiconductor devices and the output impedance of the semiconductor device are not matched, the data waveform becomes dull during transmission to cause overshoot or undershoot, thereby disabling the high-speed data transfer.
For matching the impedance of the transmission line and the output impedance of the output circuit that drives the transmission line, it is necessary that the output impedance of the semiconductor device be adjusted so as to match with the impedance of the transmission line. The output impedance of the semiconductor device is adjusted using a circuit normally called a calibration circuit. Such a calibration circuit is disclosed in Prior Document 1 (Japanese Unexamined Patent Application Publication (JP-A) No. Hei 07-142985), Prior Document 2 (Japanese Unexamined Patent Application Publication (JP-A) No. 2005-065249), and Prior Document 3 (Japanese Unexamined Patent Application Publication (JP-A) No. Hei 11-027132).
Prior Document 1 describes a calibration circuit comprising a reference resistance and a group of transistors and disposed between a supply voltage and a ground potential in the same manner as an output circuit. A technique is disclosed for reducing noise that is generated at the time of switching the state of the group of transistors in this calibration circuit. The calibration circuit controls the on/off states of the respective transistors on the basis of an output of a comparison circuit as a result of comparison between an output voltage and a reference voltage. The group of transistors is comprised of a group of large transistors having the same large driving capability and a group of small transistors having small driving capabilities that differ from one another.
The group of small transistors has the driving capability proportional to the binary system and switches the on/off states of the transistors one by one according to a binary counter signal. The group of large transistors is designed to reduce noise generated at the time of switching the state of the group of transistors by suppressing one-by-one switching of the on/off states of the transistors by the use of the decimal system. However, although the noise is reduced at the time of switching the state of the group of large transistors, the noise is still generated. Further, since the number of transistors that should be individually driven increases due to the decimal system, there arises a new problem that the number of driver circuits increases.
Prior Document 2 discloses a technique that the impedance is controlled by comparing an output voltage with a reference voltage and producing an impedance control code by the use of a counter, thereby controlling the on/off states of transistors. Prior Document 3 discloses an impedance matching circuit comprising pull-up/pull-down transistors and a counter circuit that performs counting according to the result of a comparison circuit. In the impedance matching circuit, the count result of the counter circuit is input into the gates of the transistors to thereby control the impedance of the transistors. However, the foregoing documents each still have a problem that noise is generated at the time of switching the on/off states of the transistors.
FIG. 1 exemplarily shows the noise generated at the time of switching the on/off states of the transistors. For example, assuming that a calibration circuit is comprised of five transistors, the current driving capabilities of these five transistors are configured to have a ratio of 16:8:4:2:1. By setting the current driving capabilities of the transistors to the ratio in accordance with the binary system in this manner, the transistors can be controlled corresponding to respective bits of a control signal. When the control signal changes from 01111 (binary notation) to 10000 (binary notation) and the most significant bit is input earlier than the other four bits, the total current driving capability of the calibration circuit changes as 15→31→16 (decimal notation) (hereinafter, signals will be expressed in binary notation while others in decimal notation).
In this manner, during the transition period when the control signal is shifted in level, there is a large change in current driving capability and thus a large change in potential occurs as noise. Conversely, when the control signal changes from 10000 to 01111 and the most significant bit is input later than the other four bits, the total current driving capability of the calibration circuit changes as 16→31→15. In this manner, during the transition period when the control signal is shifted in level, there is a large change in current driving capability and thus a large change in potential occurs as noise. Accordingly, as shown in FIG. 1, there is a problem that large noise occurs during transition periods when the control signal is shifted in level, thereby disabling accurate calibration.
In terms of removal of noise, there; is Prior Document 4 (Japanese Unexamined Patent Application Publication (JP-A) No. 2000-353941). Prior Document 4 describes producing a first sample and hold signal, a second sample and hold signal subsequent thereto, and a third sample and hold signal obtained by delaying the first sample and hold signal. The influence of noise is reduced by changing the level of the third sampling signal at a latter half of a hold interval thereof to the level of the second sampling signal by the use of level changing means.
As described above, the calibration circuit switches the on/off states of the transistors on the basis of the control signal, thereby matching the impedances. Therefore, there is the problem that the noise is generated at the time of switching the state of the transistors, thus disabling accurate calibration.